Journal
[1] G. Chatterjee, A. Das, S.V. Reddy and D. Gope, "Mesh Interpolated Krylov Recycling Method to expedite 3D Full-Wave MoM Solution for Design Variants", IEEE Transactions on Microwave Theory and Techniques, vol. 65, No. 9, pp. 3159-3171, Mar. 2017.
[2] N. Ambasana, G. Anand, D. Gope and B. Mutnury, "S-Parameter & Frequency Identification Method for ANN Based Eye-Height/Width Prediction", IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 7, No. 5, pp. 698-709, Feb. 2017.
[3] B. Nayak, S.V. Reddy and D. Gope, "Non-orthogonal 2.5D PEEC for Power Integrity Analysis of Package-Board Geometries", IEEE Transactions on Microwave Theory and Techniques, vol. 65, No. 4, pp. 1203-1214, Jan. 2017.
[4] Y. K. Negi, N. Balakrishnan, S. M. Rao and D. Gope, "Null-Field Preconditioner with Selected Far-Field Contribution for 3-D Full-wave EFIE", IEEE Transactions on Antennas and Propagation, vol. 64, No. 11, pp. 4923-4928, Nov. 2016.
[5] N. Ambasana, G. Anand, B. Mutnury and D. Gope, "Eye-Height/Width Prediction from S-Parameters using Learning Based Models", IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 6, No. 6, pp. 873-885, June 2016.
[6] A. Das and D. Gope, "Modified Separated Potential Integral Equation for Low Frequency EFIE-Conditioning", IEEE Transactions on Antennas and Propagation, vol. 64, No. 4, pp. 1394-1403, April 2016.
[7] A. Devi, M. Gandhi, K. Varghese and D. Gope, "Accelerating Method of Moments based Package-Board 3D Parasitic Extraction using FPGA", Microwave and Optical Technology Letters , vol. 58, No. 4, pp. 776-783, April 2016.
[8] G. Chatterjee, A. Das and D. Gope, "Learning-based Fast Iterative Convergence of 3D MoM via Eigen-AGMRES Method", IEEE Transactions on Antennas and Propagation, vol. 63, No. 12, pp. 5889-5893, Dec. 2015.
[9] A. Das and D. Gope, "Adaptive Mesh Refinement for Fast Convergence of EFIE-based 3D Extraction", IEEE Transactions on Components, Packaging and Manufacturing Technology , vol. 5, No. 3, pp. 404-414, March 2015.
[10] R. Oikawa, D. Gope and V. Jandhyala, "Return-Path Extraction Technique for SSO Analysis of Low-Cost Wire-Bonding BGA Packages", IEEE Transactions on Advanced Packaging , vol. 2, No. 4, pp. 677-686, April 2012.
[11] V. Jandhyala, D. Gope, S. Chakraborty, R. Murugan and S. Mukherjee, "Toward Building Full-System EMI Verification and Early Design Flows Through Full-Wave Electromagnetic Simulation", International Journal of RF and Microwave Computer-Aided Engineering, vol. 22, No. 1, pp. 104-115, Dec 2011.
[12] D. Gope, A. Ruehli and V, Jandhyala, "Solving Low-Frequency EM-CKT Problems Using the PEEC Method", IEEE Transactions on Advanced Packaging, vol. 30, Issue 2, pp. 313-320, May 2007.
[13] D. Gope, A. Ruehli and V. Jandhyala, "Speeding up PEEC partial inductance computations using a QR based algorithm", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 15, Issue 1, pp. 60-68, Jan 2007.
[14] I. Chowdhury, S. Chakraborty, V. Jandhyala, D. Gope and J. Rockway, "A combined Circuit- Electromagnetic-Fluidic computational methodology for force prediction in Lab-On-Chip environment", IEEE Transactions on Circuits and Systems, vol. 53, Issue 12, pp: 2664-2672, Dec. 2006.
[15] D. Gope, A. Ruehli, C. Yang and V. Jandhyala, "(S)PEEC: Time and frequency domain surface formulation for modeling conductors and dielectrics in combined circuit electromagnetic simulations", IEEE Transactions on Microwave Theory Tech., vol. 54, Issue 6, Part 1, pp: 2453-2464, Jun 2006.
[16] D. Gope and V. Jandhyala, "Efficient Solution of EFIE via Low-Rank Compression of Multilevel Predetermined Interactions", IEEE Transactions on. Antennas and Propagation, vol. 53, Issue 10, pp. 3324 - 3333 Oct 2005.
[17] Dipanjan Gope and Vikram Jandhyala, "Oct-Tree Based Multilevel Low-Rank Decomposition Algorithm for Rapid 3D Parasitic Extraction", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 23, Issue 11, Nov. 2004 pp. 1575 - 1580 Nov. 2004.
[18] Yong Wang, Dipanjan Gope, Vikram Jandhyala and C.J. Richard Shi, "Generalized KVL-KCL Formulation for Coupled Electromagnetic-Circuit Simulation with Surface Integral Equations", IEEE Transactions on. Microwave Theory Tech., vol. 52, no. 7, pp. 1673-1682, July 2004.
[19] D. Gope and V. Jandhyala, "PILOT: A Fast Algorithm for Enhanced 3D Parasitic Capacitance Extraction Efficiency", Microwave Optical technology Letters, Vol. 41, Issue 3, pp.169-173 May 2004.
[20] V. Jandhyala, Y. Wang, D.Gope and R. Shi, "A Surface Based Integral Equation Formulation for Coupled Electromagnetic and Circuit Simulation", Microwave Optical technology Letters, Vol. 34, No. 2, pp. 102-106, July 2002.
Book Chapter
[1] Dipanjan Gope, Swagato Chakraborty, Vikram Jandhyala, Mosin Mondal, Woupoung Kim, Souvik Mukherjee, Rajen Murugan, and Raj Nair, in Power Integrity Analysis and Management for Integrated Circuits, Raj Nair and Donald Bennett, Prentice Hall Modern Semiconductor Design Series, 2010.
Conferences
[1] S. Nayak and D. Gope, "Comparison of supervised learning algorithms for RF-based breast cancer detection", Proc. IEEE Computing and Electromagnetics International Workshop (CEM), pp. 13-14, Jun 2017.
[2] M. V. A. Rao, N. K. Kausthubha, S. Yadav, D. Gope, U. M. Krishnaswamy and P. K. Ghosh, "Automatic prediction of spirometry readings from cough and wheeze for monitoring of asthma severity", Proc. IEEE 25th Signal Processing Conference (EUSIPCO), pp. 41-45, 2017.
[3] N. Ambasana and D. Gope, "Mesh-sensitivity based decoupling capacitor sizing and placement for power delivery networks", Proc. IEEE 21st Signal and Power Integrity (SPI), pp. 1-4, May 2017.
[4] S. Kotethota, G. Hada, P. Ramaswamy and D Gope, "Feasibility of single wire communication for PCB-level interconnects", Proc. IEEE 21st Signal and Power Integrity (SPI), pp. 1-4, May 2017.
[5] Y. K. Negi, N. Balakrishnan, S. M. Rao and D. Gope, "Schur Complement Preconditioner For Fast 3D Fullwave MoM Package-Board Extraction", to appear Proc. IEEE conference on Electrical Design of Advanced Packaging and Systems, Dec 2016.
[6] B. Nayak, S.V. Reddy and D. Gope, "Directional Hybrid FEM-MoM for Automotive System level Simulation", to appear Proc. IEEE conference on Electric. Perf. of Electron. Packaging, Oct 2016.
[7] N. Ambasana, B. Nayak and D. Gope, "Mesh-based Impedance Sensitivity Formulation for DC/AC Power Integrity Design and Diagnosis", to appear Proc. IEEE conference on Electric. Perf. of Electron. Packaging, Oct 2016.
[8] A. Gaonkar, Bhuthesh, D. Gope and P. K. Ghosh, "Robust real-time pulse rate estimation from facial video using sparse spectral peak tracking", Proc. IEEE International Conference on Signal Processing and Communications, pp. 1-5, June 2016.
[9] H. Muniganti and D. Gope, "MIEMS: Multilevel Inverse EM Solver for 3D Image Reconstruction towards Radio-Frequency based Breast Cancer Detection", Proc. IEEE International Symposium on Antennas and Propagation, pp. 1483-1484, June 2016.
[10] B. Nayak, S.V. Reddy and D. Gope, "Extension of 2.5D PEEC for coplanar structures in power distribution network analysis", Proc. IEEE Workshop on Signal and Power Integrity, pp. 1-4, May 2016.
[11] D. Gope, G. Chatterjee, A. Das and N. Ambasana, "Smart Design Specific Electromagnetic Solvers for Chip-Package-Systems", to appear Proc. IEEE Asia-Pacific Symposium on Electromagnetic Compatibility, (invited) May 2016.
[12] A. Das and D. Gope, "Modified SPIE Formulation For Low-Frequency Stability Of Electric Field Integral Equation", Proc. IEEE Applied Electromagnetics Conference, pp. 1-2, December 2015.
[13] G. Chatterjee and D. Gope, "Krylov Recycling Method For 3D Full-Wave EM Simulation", Proc. IEEE Applied Electromagnetics Conference, pp. 1-2, December 2015.
[14] B. Nayak, S.V. Reddy and D. Gope, "Non-orthogonal 2.5D PEEC for Power Integrity Analysis", Proc. IEEE conference on Electrical Design of Advanced Packaging and Systems, pp. 174-177, December 2015.
[15] N. Ambasana, G. Anand, B. Mutnury and D. Gope, "Automated Frequency Selection for Machine-Learning based EH/EW prediction from S-Parameters", Proc. IEEE conference on Electric. Perf. of Electron. Packaging, pp. 53-56, October 2015.
[16] N. Ambasana, B. Mutnury and D. Gope, "Intelligent Rapid Investigation of S-parameters (IRIS)", (student software demonstration prize) Proc. IEEE conference on Electric. Perf. of Electron. Packaging, pp. 63-66, October 2015.
[17] G. Chatterjee, A. Das and D. Gope, "Accelerated 3D MoM Solution of Adaptively Refined Successive New Meshes on Package-Board Geometry", Proc. IEEE MTT-S International Conference on Numerical Electromagnetic and Multiphysics Modeling and Optimization, pp. 1-3, August 2015.
[18] H. Muniganti and D. Gope, "Leveraging prior state in 3-D full-wave RF imaging via Levenberg-Marquardt algorithm", IEEE Computational Electromagnetics International Workshop (CEM), pp. 1-2, July 2015.
[19] A. Das and D. Gope, "A separated potential integral equation for low-frequency PMCHWT", IEEE Computational Electromagnetics International Workshop (CEM), pp. 1-2, July 2015.
[20] G. Chatterjee, A. Das and D. Gope, "Fast Incremental 3D Full-Wave Analysis for Package-Board Design Iterations via Eigen-GCR", Proc. IEEE conference on Electrical Design of Advanced Packaging and Systems, pp. 25-28, December 2014.
[21] N. Ambasana, G. Anand, B. Mutnury and D. Gope, "Eye-Height/Width Prediction from S-Parameters using Bounded Size Training Set for ANN", (best student paper award) Proc. IEEE conference on Electrical Design of Advanced Packaging and Systems, pp. 17-20, December 2014.
[22] Y.K. Negi, N. Balakrishnan, S.M. Rao and D. Gope, "Null Field Preconditioner For Fast 3D Full-wave MoM Package-Board Extraction", Proc. IEEE conference on Electrical Design of Advanced Packaging and Systems, pp. 57-60, December 2014.
[23] G. Chatterjee, A. Das and D. Gope, "Fast Convergence of MoM-based Package-Board Extraction via Incremental Eigen-AGMRES Method", Proc. IEEE conference on Electric. Perf. of Electron. Packaging, pp. 151-154, October 2014.
[24] N. Ambasana, G. Anand, B. Mutnury and D. Gope, "Application of Artificial Neural Network for Eye-Height/Width Prediction from S-Parameters", Proc. IEEE conference on Electric. Perf. of Electron. Packaging, pp. 99-102, October 2014.
[25] A. Das, R. Nair and D. Gope, "Efficient Adaptive Mesh Refinement for MoM-based Package-Board 3D Full-wave Extraction", Proc. IEEE conference on Electric. Perf. of Electron. Packaging, pp. 239-242, October 2013.
[26] N. Ambasana, A. Chandrashekhar and D. Gope, "Application of Qualitative Imaging Methods to Electrical Performance-Aware Package Board Design", Proc. IEEE conference on Electric. Perf. of Electron. Packaging, pp. 247-250, October 2013.
[27] D. Gope, S. Chatterjee, D. De Araujo, S. Chakraborty, J. Pingenot and R. Camposano, "Device Physics aware 3D Electromagnetic Simulation of Through-Silicon-Vias in System Modeling" Proc. IEEE International 3D Systems Integration Conference, October 2013.
[28] A. Devi, M. Gandhi, K. Varghese and D. Gope, "Hardware accelerator for 3D method of moments based parasitic extraction", Proc. IEEE conference on Electrical Design of Advanced Packaging and Systems, pp. 100-103, December 2013.
[29] A. Das and D. Gope, "Hybrid Aggregated-Vector Algorithm for Efficient Parallelization of Fast Multipole Method", Proc. IEEE meeting on Electric. Perf. of Electron. Packaging, pp. 181-184, Oct. 2012.
[30] V. P. Padhy, N. Balarishnan, D. Gope, "Solving volume integral equation using ScaLAPACK", Proc. Mathematical Methods in Electromagnetic Theory, pp. 288-291, Aug. 2012.
[31] R. Murugan, S. Mukherjee, M. Mi, L. Pauc, C. Girardi, D. Gope, D. de Araujo, S. Chakraborty, and V. Jandhyala, "System-level SoC Near-Field (NF) Emissions: Simulation to Measurement Correlation", Proc. IEEE Electronic Components and Technology Conference, pp. 140-146, May 2012.
[32] R. Camposano, D. Gope, S. Grivet-Talocia and V. Jandhyala, "Moore meets Maxwell", Proc. IEEE Design Automation and Test in Europe, pp. 1275-1276, March 2012.
[33] D. Gope, V. Jandhyala, X. Wang, D. Macmillen, R. Camposano, S. Chakraborty, J. Pingenot, and D. Williams, "Towards System-Level Electromagnetic Field Simulation on Computing Clouds", Proc. IEEE meeting on Electric. Perf. of Electron. Packaging, pp. 167-170, October 2011.
[34] R. Oikawa, D. Gope, and V. Jandhyala, "Broadband SSO modeling for a weak signal return-path system based on the large-scale signal-power combined three-dimensional full-wave BEM solver model", Proceedings of the IEEE Electrical Components and Technology Conference, pp. 638-645, Las Vegas, June 2010.
[35] V. Jandhyala, S. Chakraborty and D. Gope, "Next-generation three-dimensional full-wave electromagnetic solver hybridization for large-scale signal integrity, power integrity, and EMI modeling", Proc. International Symposium on EMC, pp. 407-412, Aug. 2010.
[36] R. Murugan, S. Chakraborty, S. Mukherjee, D. Gope, and V. Jandhyala, "Building IC-package-PCB-system EMI/EMC verification and early design flows: Challenges and methods", Proceedings of DESIGNCON conf., Santa Clara, February 2010.
[37] S. Mukherjee, D. Gope, R. Murugan, S. Chakraborty, and V. Jandhyala, "An accurate methodology for model-to-hardware calibration and correlation with PCB-package simulation using electromagnetic field solvers", Proceedings of DESIGNCON conf., Santa Clara, February 2010.
[38] A.V. Sathanur, R. Chakraborty, V. Jandhyala, F. Ling, D. Gope and S. Chakraborty "An accurate hierarchical electromagnetic-circuit technique for statistical analysis of RF circuits", Proc. International Symposium of IEEE APS/URSI, pp. 1-4, July 2008.
[39] Chuanyi Yang, S. Chakraborty, D. Gope and V. Jandhyala, "3D accelerated electromagnetic integral equation solvers on parallel processors for microelectronic simulation", Proc. International Symposium on EMC, pp. 539-543, Aug. 2006.
[40] Chuanyi Yang, Dipanjan Gope and Vikram Jandhyala, "A parallel low-rank matrix compression algorithm for parasitic extraction of electrically large structures", Proc. IEEE Design Automation Conference, pp. 1053-1056, July 2006.
[41] Vikram Jandhyala, Swagato Chakraborty, Dipanjan Gope, Chuanyi Yang, Indroneil Chowdhury and Gong Ouyang, "Accelerated, parallelized time and frequency domain simulators for complex high-speed micro-systems", Proc. IEEE International Symposium of APS 2005 Conference, pp. 123-126, 2006.
[42] Dipanjan Gope, Albert Ruehli and Vikram Jandhyala, "Solving Low Frequency EM-CKT Problems Using the PEEC Method", Proc. IEEE meeting on Electric. Perf. of Electron. Packaging, Austin, pp. 351-354, October 2005.
[43] Swagato Chakraborty, Dipanjan Gope, Gong Ouyang and Vikram Jandhyala, "Three-stage Preconditioner for Modeling Electromagnetic Components in Integrated Packages with Arbitrary Boundary Contours", Proc. IEEE meeting on Electric. Perf. of Electron. Packaging, Austin, pp. 199-202, October 2005.
[44] Chuanyi Yang, Swagato Chakraborty, Dipanjan Gope, Gong Ouyang and Vikram Jandhyala, "A Parallel Multilevel Low-Rank Decomposition Algorithm for Fast Simulation of High-Speed Electronic Interconnect and Packages", Proc. IEEE meeting on Electric. Perf. of Electron. Packaging, Austin, pp. 245-248, October 2005.
[45] Vikram Jandhyala, Swagato Chakraborty, Dipanjan Gope, and Chuanyi Yang, "Accelerating Coupled Circuit-EM Simulation in the Frequency and Time Domain", Proc. International Symposium on IEEE EMC, vol. 3, pp 823-827, 2005.
[46] Vikram Jandhyala and Dipanjan Gope, "Fast Full-wave Electric and Magnetic Field Integral Equation Solvers based on QR Compression of Predetermined Matrices", Proc. ICEEA Italy 2005.
[47] V. Jandhyala, S. Chakraborty, D. Gope, and C. Yang, "Fast Methods for Electromagnetic and Circuit-Electromagnetic Simulation of Mixed-Signal Systems and High-Speed ICs in Time and Frequency Domains", Proc of the 12th International Conference on Mixed Design of Integrated Circuits and Systems (Mixdes), invited plenary talk, pp. 715-719, June 2005.
[48] Dipanjan Gope, Indranil Chowdhury and Vikram Jandhyala, "DiMES: Multilevel Fast Direct Solver Based on Multipole Expansions for Parasitic Extraction of Massively Coupled 3D Microelectronic Structures", Proc. IEEE DAC Anaheim 2005 Conference, pp. 159-162.
[49] Dipanjan Gope and Vikram Jandhyala, "Fast Full-wave EFIE Solution by Low-rank Compression of Multilevel Pre-determined Sub-matrices", Proc. IEEE International Symposium of APS 2005 Conference, 2005.
[50] Albert Ruehli, Dipanjan Gope and Vikram Jandhyala, "Mixed Volume and Surface PEEC Circuit and Electromagnetic Solver", Proc. International Symposium on EMC Zurich Conf. 2005.
[51] Dipanjan Gope, Albert Ruehli and Vikram Jandhyala, "Surface-based PEEC Formulation for Modeling Conductors and Dielectrics in Time and Frequency Domain Combined Circuit Electromagnetic Simulations", Proc. IEEE meeting on Electric. Perf. of Electron. Packaging, Boston, pp. 329-332, October 2004.
[52] Albert Ruehli, Dipanjan Gope and Vikram Jandhyala, "Block Partitioned Gauss-Seidel PEEC Solver Accelerated by QR based Coupling Matrix Compression Techniques", Proc. IEEE meeting on Electric. Perf. of Electron. Packaging, Boston, pp. 325-328, October 2004.
[53] Dipanjan Gope, Swagato Chakraborty and Vikram Jandhyala, "A fast parasitic extractor based on low-rank multilevel matrix compression for conductor and dielectric modeling in microelectronics and MEMS", IEEE Design and Automation Conference, pp. 794-799, 2004.
[54] Albert Ruehli, Dipanjan Gope and Vikram Jandhyala, "Mixed Volume and Surface PEEC Modeling", Proc. International Symposium of IEEE APS/URSI, 2004.
[55] D.Gope and V.Jandhyala, "PILOT: A Fast Algorithm for Enhanced 3D Parasitic Capacitance Extraction Efficiency", IEEE meeting on Electric. Perf. of Electron. Packaging, Princeton, pp. 337-340, Oct. 2003.
[56] Yong Wang, Dipanjan Gope, Vikram Jandhyala, and C.J. Richard Shi, "Integral Equation-based Coupled Electromagnetic-Circuit Simulation in the Frequency Domain", Proc. IEEE International Symposium of APS-URSI, Ohio, vol. 3, pp. 328-331, June 2003.
[57] Dipanjan Gope and Vikram Jandhyala, "Fast Direct Solver for Massively Coupled Parasitic Extraction Problems", SRC TechCon Technical Digest, Dallas, August 2003.
[58] Y. Wang, D. Gope, V. Jandhyala and C.J. Shi, "Integral Equation-based Coupled Electromagnetic-Circuit Simulation in the Frequency Domain", SRC TechCon Technical Digest, Dallas, August 2003.
Awarded Best Paper in Session (Mixed Signal Technology).
[59] V. Jandhyala, Yong Wang, D. Gope, S. Chakraborty and R. Shi, "A Surface-Integral Equation Based Technique for General Coupled Circuit Electromagnetic Simulation", Proc. Progress in Electromagnetic research Symposium, Boston, July 2002.
[60] D.Gope, S. Chakraborty, Y.Wang, Vikram Jandhyala and Richard Shi, "A Surface Based 3D Coupled Circuit Electromagnetic Simulator with Accurate Lossy Conductor Modeling", Proc. IEEE International Symposium of APS-URSI, San Antonio, June 2002.
[61] V. Jandhyala, Y. Wang, D. Gope and R. Shi, "Coupled Electromagnetic-Circuit Simulation of Arbitrarily Shaped Conducting Structures Using Triangular Meshes", Proc. International Symposium on Quality electronic Design, San Jose, pp. 38-42, March 2002.
[62] Dipanjan Gope and Vikram Jandhyala, "An Iteration-Free Fast Multilevel Solver for Method of Moments Systems", Proc. IEEE meeting on Electric. Perf. of Electron. Packaging, Boston, pp. 177-180, October 2001.
[63] Dipanjan Gope and Vikram Jandhyala, "A Fast, Direct, Multiple Right-Hand Side Solver for the Method of Moments", Proc. IEEE International Symposium of APS-URSI, June 2001.
Other Articles
[1] V. Jandhyala, D. Gope, S. Chakraborty, F. Ling, X. Wang, D. Williams and J. Pingenot, "3D Chip-Package-Board Modeling",
Printed Circuit Design and Fab., pp. 24-28, Nov 2008.
Patents
[1] V. Jandhyala, S. Chakraborty and D. Gope, Adaptive redundancy-extraction for 3D electromagnetic simulation of electronic systems, US8725484 B2, Issued May 13, 2014.
[2] V. Jandhyala, S. Chakraborty, D. Gope and F. Ling, Mixed Decoupled Electromagnetic Circuit Solver, US20090177456 A1, Issued July 9, 2009.